Phase-locked loops (PLLs) are essential parts of practically all of today's electronic systems like wireless transceivers, data converters, or digital systems. The main PLL performance metrics are area consumption, tuning range, and jitter performances. In a modern electronic system, many PLLs need to be integrated, such that area consumption, tuning range, and jitter performances of PLLs are also critical to the system.
From area and tuning range perspectives, ring oscillator (RO) based PLLs are more attractive than inductor-capacitor (LC) oscillator based PLLs, since the RO based PLLs avoid large on-chip inductors. However, RO based PLLs tend to have poor jitter or noise performance. The jitter of a PLL can be broadly classified as a random jitter (RJ) that arises from device noise and manifests itself as phase-noise side bands around the carrier, and a deterministic jitter (DJ) that arises due to periodic disturbances from the reference clock and manifests itself as reference spurs.
To reduce the total jitter (both the phase noise and reference spurs) and to utilize the area and tuning range advantages of a RO based PLL, it is therefore an object of the present disclosure to provide a compact PLL design with better jitter performances. Further, there is also a need for the final product to have low power consumption.